Conjugate Heat Transfer: Coupling CFD with Solid Conduction in Electronic Cooling
Conjugate heat transfer is how heat moves through both hot electronics (solid parts) and the cooling air or liquid around them — all at the same time, like baking a cake while blowing a fan over it.
⚠️ Why It Matters
📘 Definition
Conjugate heat transfer (CHT) is the simultaneous solution of heat conduction in solids and convective heat transfer in fluids, enforcing thermal continuity and flux balance at solid–fluid interfaces. It is governed by the Fourier law for solids, the Navier–Stokes and energy equations for fluids, and interfacial coupling conditions for temperature and heat flux. Unlike decoupled approaches, CHT resolves bidirectional thermal interaction without prescribed boundary temperatures or heat transfer coefficients.
🎨 Concept Diagram
AI-generated illustration for visual understanding
💡 Engineering Insight
Never assume 'adiabatic' or 'isothermal' boundaries on chip surfaces — real-world die attach non-uniformity and trace current crowding create thermal gradients >15°C/mm that invalidate lumped-resistor models. Always resolve at least one full copper layer beneath active devices, even if simplified as a homogeneous orthotropic solid.
📖 Detailed Explanation
Unlike traditional '1D fin' or 'thermal resistance network' methods, CHT solves the full energy equation simultaneously in both domains, capturing recirculation zones, bypass flows, and thermal shadowing — effects that cause standard correlations (e.g., Dittus–Boelter) to err by ±40% in complex enclosures. Interface coupling enforces both temperature continuity (T_solid = T_fluid) and flux balance (−k_s ∂T_s/∂n = −k_f ∂T_f/∂n), eliminating artificial 'wall functions' or guessed h-values.
Advanced CHT includes radiation exchange between non-isothermal surfaces (e.g., heatsink fins to enclosure walls), phase-change effects in two-phase cold plates, anisotropic conductivity in layered substrates (e.g., SiC MOSFET packages), and dynamic coupling to electrothermal models where resistivity changes with local T — essential for predicting electromigration lifetime and voltage droop under load transients.
🔄 Engineering Workflow
📋 Decision Guide
| Rock/Field Condition | Recommended Design Action |
|---|---|
| High-power ASIC (>300 W) on low-k PCB (k < 0.5 W/m·K) with natural convection | Replace FR-4 with metal-core PCB or embedded copper planes; add vapor chamber; avoid passive-only cooling |
| Transient operation (e.g., radar pulse, AI inference burst) with >100 W/s dP/dt | Enable CHT with transient solver + solid thermal capacitance; include TIM compressibility and contact conductance hysteresis |
| Liquid-cooled cold plate with microchannels and silicon dies directly bonded | Use fully coupled CHT with conjugate meshing at die–TIM–cold plate interface; resolve sub-10 µm TIM gaps with local prism layer |
📊 Key Properties & Parameters
Thermal Conductivity (k_solid)
1–400 W/m·K (e.g., FR-4: 0.3; Al6061: 167; Cu: 390)Material property quantifying how well a solid conducts heat by conduction (W/m·K).
Low k_solid in PCB substrates causes localized hot spots that drive premature semiconductor failure.
Heat Transfer Coefficient (h)
5–250 W/m²·K (natural convection: 5–25; forced air: 25–150; liquid cooling: 100–250)Empirical measure of convective heat transfer intensity at a surface (W/m²·K).
Underestimating h due to flow maldistribution leads to 15–30°C unmodeled temperature rise at critical ICs.
Interfacial Thermal Resistance (R_int)
0.1–50 × 10⁻⁶ m²·K/W (e.g., high-performance grease: 0.5; voided solder: 15; air gap: >30)Thermal resistance across bonded or contact interfaces (e.g., TIM, solder, die attach) per unit area (m²·K/W).
A 5× increase in R_int can elevate CPU junction temperature by >20°C even with perfect airflow design.
Solid-to-Fluid Conduction Length Ratio (L_s/L_f)
0.05–5.0 (e.g., chip-on-board: ~0.1; cold plate with embedded channels: ~2.5)Dimensionless ratio comparing characteristic conduction path length in solid to fluid domain size.
Ratios <0.2 indicate dominant fluid-side resistance; >2.0 imply solid conduction dominates and requires mesh refinement in substrate layers.
📐 Key Formulas
Interface Heat Flux Balance
q'' = -k_s \frac{\partial T_s}{\partial n} = -k_f \frac{\partial T_f}{\partial n}Ensures conservation of energy across solid–fluid interface
| Symbol | Name | Unit | Description |
|---|---|---|---|
| q'' | Interface Heat Flux | W/m² | Heat flux at the solid-fluid interface |
| k_s | Solid Thermal Conductivity | W/(m·K) | Thermal conductivity of the solid phase |
| k_f | Fluid Thermal Conductivity | W/(m·K) | Thermal conductivity of the fluid phase |
| T_s | Solid Temperature | K | Temperature field in the solid phase |
| T_f | Fluid Temperature | K | Temperature field in the fluid phase |
| n | Normal Direction | Direction normal to the solid-fluid interface |
Effective Thermal Resistance (R_th,eff)
R_{th,eff} = \frac{T_{junction} - T_{inlet}}{P_{dissipated}}System-level thermal resistance from junction to coolant inlet
| Symbol | Name | Unit | Description |
|---|---|---|---|
| R_{th,eff} | Effective Thermal Resistance | K/W | System-level thermal resistance from junction to coolant inlet |
| T_{junction} | Junction Temperature | K | Temperature at the semiconductor junction |
| T_{inlet} | Coolant Inlet Temperature | K | Temperature of the coolant at the inlet |
| P_{dissipated} | Dissipated Power | W | Power dissipated by the device |
🏭 Engineering Example
NVIDIA DGX A100 Server (2020 Design Revision)
Not applicable — electronic system- Data center GPU thermal management
- Automotive SiC inverter cooling
- Avionics high-density VPX cooling
- 5G mmWave RF front-end thermal design
📋 Real Project Case
Air-Cooled Condenser Retrofit for 600 MW Coal Power Plant
Retrofit of legacy water-cooled condenser at Midwest US plant